The deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, contact resistance becomes more significant and needs to be reduced.
The principle way of reducing contact resistances between polysilicon gates and source/drain regions and interconnect lines is by forming metal silicides atop the source/drain regions and the gate electrodes prior to the formation of various conductive interconnect lines. Silicide regions are typically formed by a self-aligned silicide (salicide) process. In the salicide process, a thin layer of metal is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming metal silicide regions. The process is referred to as a self-aligned silicidation process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrodes. Following the formation of the silicide regions, the un-reacted metal is removed and an interconnection formation process is performed to provide conductive paths. A typical interconnection formation process includes the step of forming via holes through a deposited interlayer dielectric and filling the via holes with a conductive material, e.g., tungsten.
Problems occur when the salicide processes are performed on PMOS devices, wherein their source/drain regions are often formed of SiGe. It is harder for silicon germanium than silicon to react with metal, and the roughness of germano-silicide is greater than the roughness of silicide. In addition, the sheet resistance of germano-silicide is significantly greater than the sheet resistance of silicide. This is particularly true if the salicide processes are performed at low temperatures, such as 600° C. or less. In order to reduce the sheet resistance and to reduce the profile of (germano-) silicide, new methods for improving the silicide formation process of MOS devices are needed.